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On Tue, 14 Dec 2004, Ingo Molnar wrote:
> find the correct patch below. I've tested it with an NMI watchdog
> frequency artificially increased to 10 KHz, and i've instrumented the
> new branch in the NMI handler, but even under heavy IRQ load i was not
> able to trigger the branch. Maybe newer CPUs handle this case somehow
> and make sti;hlt truly atomic?
Now that you mention it, I have this dim memory of the one-instruction
"sti-shadow" actually disabling NMI's (and debug traps) too. The CPU
literally doesn't test for async events following "sti".
Or maybe that was "mov->ss". That one also has that strange "black hole"
for one instruction.
Hmm.. You could be evil and try to fill up 64kB worth of memory with a
"mov %ax,%ss", and jump to it in vm86 mode and see what happens. The eip
will just keep wrapping around...
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